Digital Design Automation – EN0720 | My Assignment Tutor

Digital Design Automation – EN0720 (KD7020)Assignment 1 2020-21Design, Verification and Implementation of an FPGA-based Monitoring SystemObjectives:• To create SystemVerilog (SV) design source descriptions for the various component partsof a Monitoring System comprising an Analogue-to-Digital Converter, Asynchronous SerialData Transmitter and Receiver along with a display.• To incorporate an IP (Intellectual Property) module into the design using customisation andinterfacing.• To perform simulations of individual design modules using SV test-modules and theVivado® Simulator.• To perform simulations of the complete Monitoring System top-level module using a SVtest-module and the Vivado® Simulator.• Synthesise and Implement the Monitoring System, targeting a Field Programmable GateArray development board (Artix-7 FPGA on Digilent® Basys3® development board).• Demonstrate the operation of the FPGA implementation of the Monitoring System using theBasys3® development board by means of a so-called ‘hardwired loop-back’ test.Learning Outcomes:See Assignment Specification document:‘EN0720_KD7020_assignment_2020_21_Specification_part1.docx’.Software and Hardware Resources:• Xilinx Vivado ® FPGA/CPLD Design Suite. Available in labs E204/206 and as a freedownload (Vivado HLS WebPACK Edition) from: http://www.xilinx.com/products/designtools/vivado/vivado-webpack.html• Digilent® Incorporated ‘Basys3’ Artix-7 FPGA Development Board. Reference Manual.Supporting Documentation (available on eLearning portal)• Powerpoint presentation on Register Transfer Level Design using the SystemVeriloghardware description language. See document on eLearning: ‘RTL with SystemVerilog2016.pdf’.• Workshop exercise on ‘XADC’ built-in Analogue-to-Digital Converter (Workshop 4), seedocument: ‘XADC_Display_SV_2019.pdf’Total number of marks available: 120Assignment 1 – Description of the Monitoring SystemFigure 1, below, shows a simplified block diagram of the Monitoring System and figure 2 showsthe corresponding physical layout of the Basys3 development board.The system is driven by a 100MHz crystal clock and an active-high reset push button, when thelatter is pressed, the entire system is reset. The main functional blocks that make up the systemare shown in figure 1: i.XADC – built-in Analogue-to-Digital Converter that can be instantiated from the IP library.The analogue input voltage range is 0.0 to +1.0 Volts.XADC Controller – responds to manual or timer generated pulses initiating an ADCconversion, it produces the required control signals for the XADC and interfaces with thetransmitter.Transmitter – after each conversion, the 12-bit result is transmitted over an asynchronousserial data link as an individual character.Receiver – receives the asynchronous character from the transmitter and displays the valueii.iii.iv. on the 7-segment display.This assignment involves the design, verification and implementation of the Monitoring Systemusing a Field Programmable Gate Array (FPGA) device, this is achieved through a series ofguided tasks.Transmitter ReceiverTxData RxInAnalogue InputXADCControllerTimerAsynchronous Serial LinkDisplayStatus LEDsXADCFigure 1 – Simplified block diagram of the Monitoring SystemThe physical layout of the Monitoring System implemented using the Digilent® ‘Basys3’development board, shown in figure 2, illustrates the location of the main inputs and outputs.RESETTxOut(JB1)RxIn (JB4)Analogue InputJAswAuto_Man, ONETx, ONERx, RBManTo R-2R DACTxBusy, PE, FEand BF LEDsFigure 2 – Physical layout of the Monitoring System on Basys3 BoardFigure 3, below, is a more detailed internal block diagram of the Monitoring System. The shadedblocks shown in figure 3 are implemented within the Artix-7 FPGA device. The 4-digit, 7-segmentdisplay, R-2R ladder network Digital-to-Analogue Converter, clock generator and various buttonsand switches are located on the Basys3 board and connected to specific FPGA pins as specifiedin the ‘*.xdc’ (Xilinx Design Constraint) file.Figures 3a and 3b show the left- and right-hand sides of the system in more detail.Figures 3 (3a and 3b) shows the FPGA pin designators next to each input/output terminal, forexample, the transmitter output ‘TxData’ is allocated FPGA pin ‘A14’, and this in turn is connectedto header connector ‘JB1’, as shown in figure 2.The R-2R DAC, shown at the top left-hand corner of figure 3, is an external plug-in ‘PMOD’module. This is used to produce a test voltage for input to the XADC, the value of which is set bythe eight sliding switches ‘SW0..7’. When testing the Basys3 board it is important to ensure theswitches are set such that the test voltage is within the range of the XADC unipolar input, i.e. 0.0to +1.0 Volts.Careful study of all three figures (3, 3a and 3b) will reveal that interconnecting signal names andmodule port names have been matched throughout the design (see red box in figure 3a), with oneor two exceptions. This allows the use of the SystemVerilog automatic port connection feature,considerably shortening and simplifying the source descriptions. Busy, pbuffer_farity_error andull LEDs TxData (JB1)(read_buffer)Figure 3 – Detailed block diagram of the Monitoring SystemFigure 3a – XADC, Controller and serial Transmitter16’b0data[0..11] data_rx[0..15]daddr_in[0..6]do_out[0..15] bcd[0..3]sel[1:0]AN0(U2)AN1(U4)AN2(V4)AN3(W4)CA(W7)CB(W6)CC(U8)CD(V8)CE(U5)CF(V5)CG(U7)DP(V7)den_indrdy_outeoc_outconvst_inCLK100M (W5)RESET (U18)Vin~q1q0clockresetwritePulseMPtriggerXADCJ3 vauxp6K3 vauxn6reset_inconvst_inalarm_outeos_outeoc_outbusy_outdrdy_indclk_indwe_inden_indo_out[0..15]di_in[0..15]daddr_in[0..6]vn_in channel_out[0..4]vp_inX1XADC0DADDR selects ADC status (result) registerAddress of Vauxp/n[6] result register is 7’h16ADCCLK is DCLK divided by 4 = 25MHzdisp_cntrclockresetAN0AN1AN2AN3sel[0..1]U6DISP_CNTRbcd2segA B C D E F Gbcd[0..3]dispmuxsel[0..1]data_rx[0..15]bcd[0..3]clockresetbuffer_fullActive-low cathodesActive-low anodesAN3 is most-significant digit (leftmost)JXADCVCC GND vauxp6vauxn66 5 4 3 2 112 11 10 9 8 7vauxp14vauxn14vauxp7vauxn7vauxp15vauxn15VCC GNDTimerclockresetPulseXADC_Controller_txtriggerdo_out[0..15] data[0..11]daddr_in[0..6]den_indrdy_outeoc_outconvst_inclockresetwriteR110kR210kR310kR410kR510kR610kR710kR810kR920kR1020kR1120kR1220kR1320kR1420kR1520kR1620kSW7SW-SPDTSW6SW-SPDTSW5SW-SPDTSW4SW-SPDTSW3SW-SPDTSW2SW-SPDTSW1SW-SPDTSW0SW-SPDTW13 W14 V15 W15 W17 W16 V16 V17BTNDManR1710kR1810kU17Use push-button OR TimerCLKDQ!QRESETSETU3DTFFCLKDQ!QRESETSETU4DTFFTxSysRTLclockresetodd_notevenwritedata[0..11]BusyTxDataRxSysRTLclockresetodd_notevenread_bufferdata_rx[0..16]buffer_fullRxInparity_errorTxData (A14) RxIn (B16)parameters:CLKSPERBIT = 20,BITSPERCHAR = 15,BTn = 5,BCn = 4,DATABITS = 12ONETx (T1)read_buffer (W2)Busy (V19)parity_error (U16)buffer_full (U19)ONERx (U1)M0 1Auto_Man (R2) s parameters:NUMCLKS = (500)10000,n = (9)14parameter:N = 216’b0data[0..11]daddr_in[0..6]do_out[0..15]den_indrdy_outeoc_outconvst_inCLK100M (W5)RESET (U18)Vin~q1q0clockresetwritePulseMPtriggerXADCJ3 vauxp6K3 vauxn6reset_inconvst_inalarm_outeos_outeoc_outbusy_outdrdy_indclk_indwe_inden_indo_out[0..15]di_in[0..15]daddr_in[0..6]vn_in channel_out[0..4]vp_inX1XADC0DADDR selects ADC status (result) registerAddress of Vauxp/n[6] result register is 7’h16ADCCLK is DCLK divided by 4 = 25MHzJXADCVCC GND vauxp6vauxn66 5 4 3 2 112 11 10 9 8 7vauxp14vauxn14vauxp7vauxn7vauxp15vauxn15VCC GNDTimerclockresetPulseXADC_Controller_txtriggerdo_out[0..15] data[0..11]daddr_in[0..6]den_indrdy_outeoc_outconvst_inclockresetwriteR110kR210kR310kR410kR510kR610kR710kR810kR920kR1020kR1120kR1220kR1320kR1420kR1520kR1620kSW7SW-SPDTSW6SW-SPDTSW5SW-SPDTSW4SW-SPDTSW3SW-SPDTSW2SW-SPDTSW1SW-SPDTSW0SW-SPDTW13 W14 V15 W15 W17 W16 V16 V17BTNDManR1710kR1810kU17Use push-button OR TimerCLKDQ!QRESETSETU3DTFFCLKDQ!QRESETSETU4DTFFTxSysRTLclockresetodd_notevenwritedata[0..11]BusyTxDataTxData (A14) RxIn (B16)parameters:CLKSPERBIT = 20,BITSPERCHAR = 15,BTn = 5,BCn = 4,DATABITS = 12ONETx (T1)read_buffer (W2)Busy (V19)ONERx (U1)M0 1Auto_Man (R2) s parameters:NUMCLKS = (500)10000,n = (9)14Figure 3b – Serial Receiver and DisplayFigure 4 shows the timing format for the characters being transmitted by the ‘TxSysRTL’ module,(transmitter) on the serial data output ‘TxData’, and received by the ‘RxSysRTL’ (receiver) blockon the serial data input ‘RxIn’.The most-significant 12-bits of each 16-bit result from the A-to-D converter is embedded within adata character having a start-bit, parity-bit (odd or even) and one or more stop-bits, in the samemanner as a UART (Universal Asynchronous Receiver-Transmitter).To allow synchronisation between transmitter and receiver, each individual serial bit has a durationset by the ‘CLKSPERBIT’ parameter. In between data character transmissions, the serialcommunication line remains high.TxData 0 1 2 3TxBusyStartBitDATABITS-1DATABITS-2ParityBit Stop Bit(s)One Character (BITSPERCHAR bits)CLKSPERBIT(DATABITS bits)Figure 4 – Format of Asynchronous Serial Data CharacterThe transmitter also outputs a ‘TxBusy’ signals which goes high at the falling edge of the start-bitand returns to logic-0 at the end of the last stop-bit (after ‘BITSPERCHAR’ bits). This signal can beused to prevent a transmitting data source from attempting to send data prior to the end of thecurrent transmission. The ‘DATABITS’ parameter sets the number of data bits in the character,data_rx[0..15] bcd[0..3]sel[1:0]AN0(U2)AN1(U4)AN2(V4)AN3(W4)CA(W7)CB(W6)CC(U8)CD(V8)CE(U5)CF(V5)CG(U7)DP(V7)disp_cntrclockresetAN0AN1AN2AN3sel[0..1]U6DISP_CNTRbcd2segA B C D E F Gbcd[0..3]dispmuxsel[0..1]data_rx[0..15]bcd[0..3]clockresetbuffer_fullActive-low cathodesActive-low anodesAN3 is most-significant digit (leftmost)RxSysRTLclockresetodd_notevenread_bufferdata_rx[0..16]buffer_fullRxInparity_errorTxData (A14) RxIn (B16)(W2)Busy (V19)parity_error (U16)buffer_full (U19)(U1)parameter:N = 2and this along with the other two parameters shown in figure 4 are common (but independentlyset) to both the transmitter and receiver.The serial transmission of ADC data values can be controlled in the following ways, the first two ofthese are provided for by the circuitry shown in figures 3, 3a and 3b:i. Automatic conversion and transmission at intervals set by the Timer module. With the‘Auto_Man’ input set to logic-1, the XADC ‘trigger’ input (triggers a conversion) receivespulses from the Timer module at intervals set by the Timer parameter ‘NUMCLKS’ (numberof 100MHz clock pulses). ii.Manual conversion and transmission invoked by the ‘Man’ pushbutton. Pressing ‘BTND’ onthe Basys3 board produces one ‘trigger’ pulse, this feature is enabled when the ‘Auto_Man’input set to logic-0.Maximum conversion and transmission rate determined by XADC conversion time and timeiii. to transmit one data character. In this mode, data characters are transmitted continuouslywith the start-bit immediately following the last stop-bit of adjacent characters.Task 1 – Create a SV source description of the ‘RxSysRTL’ moduleFigure 5 shows the ASM chart and other details relating to the receiver module ‘RxSysRTL’.The figure shows the behaviour of the module in the form of an ASM chart, along with a symbolicrepresentation and the main internal registers. The internal signal named ‘Start’ is derived from theserial data input ‘RxIn’ such that a single clock-pulse-length pulse is produced on ‘Start’ each time‘RxIn’ undergoes a logic-1 to logic-0 transition (Refer to figure 3, the ‘MP’ circuit plays a similarrole).At the bottom right hand corner of figure 5, a logic circuit is included to illustrate the operation ofthe ‘Parity’ error output (parity_error). The system enters state ‘s5’ once a complete serial datacharacter has been received (the shift register (SR) is transferred to the buffer register (BR) in theprevious state, ‘s4’) and a logic-1 is transferred to the ‘buffer_full’ output. The ‘buffer_full’ signalenables the parity circuit flip-flop to load a value from the respective logic shown on the diagram(Exclusive-OR and Nand gate).In the event of a parity error, the ‘parity_error’ output flag remains high until, either a master resetoccurs, or the next data character is receivedThe parallel data output of the receiver module ‘data_rx’ is 16-bits in length, in order to drive the 4-digit hexadecimal display logic directly. The data value received from the transmitter occupies thelower bits of this output bus.The receiver cannot receive another serial data character until the buffer is read, i.e. the‘read_buffer’ input is asserted.Appendix A contains a listing for the transmitter module ‘TxSysRTL’, in the form of aSystemVerilog register transfer level (RTL) description. Appendix B contains the correspondingASM chart for the transmitter.Using the information provided in appendices A and B, along with figure 5, create a completeRegister Transfer Level (RTL) SV source description for the receiver module, saving it in a text filenamed ‘RxSysRTL.sv’. The receiver module is to have an identical set of parameter declarationswhen compared to the transmitter module. The source file can be created within the XilinxVivado® software, alternatively Notepad++ could be used.Include a full listing of the ‘RxSysRTL’ module in your report, presented in a style consistent withthat used in Appendix A (consolas font, reserved words bold, comments in italics withappropriate use of indentation). Do not use a screen-copy of the listing as it appears within theVivado text editor.[20 marks]BR ← 0SR ← 0BC ← BITSPERCHARBT ← CLKSPERBIT/4Buffer_Full ← 0BCBTSRBRIDLEStart0BT ← BT – 11s1BT == 0?0BC ← BC – 1SR ← (RxIn, SR[BITSPERCHAR-1:1])s31s2BC == 0?0BT ← CLKSPERBIT/2 – 11Buffer_Full ← 1s5Read_buffer1 0BR ← SRBITSPERCHAR-1……0BITSPERCHAR-1……0s4ResetBit TimerBit CounterShift RegisterBuffer RegisterRxSysRTLDetectStartBitStartClkResetOdd_NEvenRead_bufferRxIn Buffer_FullParity_ErrorFraming_Errordataout[7:0]dataout = BR[DATABITS+1:1]Q QSETCLRDParity_errorResetClkBuffer_Full0 1Odd_NEvendataoutQ QSETCLRDFraming_errorResetClkBuffer_Full0 1BR[BITSPERCHAR-1:DATABITS+2]DDFigure 5 – ASM chart and information relating to the receiver module ‘RxSysRTL’data_rx[15:0]data_rx = BR[DATABITS:1]odd_notevenodd_notevenBR[DATABITS+1:1]Task 2 – Complete the test-module provided in Appendix A and verify the correct operation of theTransmitter and Receiver modulesHaving created the SV source description for the receiver in task 1, this can be combined with thetransmitter module in order to verify correct operation. The source description for the transmittermodule is provided in Appendix A – ‘TxSysRTL.sv’.Figure 6 shows a block diagram of the incomplete test-module provided in Appendix A, named‘test_TxRxSysRTL’.Note that the diagram below shows an 8-bit ‘data’ port for the purposes of simulation only.Figure 6 – block diagram of the combined module ‘test_TxRxSysRTL’.The SV source listing for the test-module (‘test_TxRxSysRTL.sv’) provided in Appendix A requiresthe addition of module-instantiation-statements and a continuous-assignment statement, with theparameters of the instantiated transmitter and receiver modules set to the values shown in figure6.Include a full listing of the ‘test_TxRxSysRTL.sv’ module source in your report, presented in a stylesimilar to that used in Appendix A (consolas font, reserved words bold, comments in italics withappropriate use of indentation). Highlight the statements you have added as detailed above.Do not use a screen-copy of the listing as it appears within the Vivado text editor.[10 marks]Use the Xilinx Vivado FPGA design software to create a new RTL project for this assignment,targeting the device on the Digilent Basys3 development board.Add the SV sources, provided and created so far, to the project. Ensure that any simulation testmodules are added/created as ‘simulation’ sources.The project should contain the following sources:‘TxSysRTL.sv’ (see Appendix A)‘RxSysRTL.sv’ (Task 1)‘test_TxRxSysRTL.sv’ (Task 2 – see Appendix A)TxSysRTLclockresetodd_notevenwritedata[0..7]BusyTxDataRxSysRTLclockresetodd_notevenread_bufferdata_rx[0..15]buffer_fullRxInparity_errorTxData RxInparameters:CLKSPERBIT = 20,BITSPERCHAR = 12,BTn = 5,BCn = 4,DATABITS = 8parameters:CLKSPERBIT = 20,BITSPERCHAR = 12,BTn = 5,BCn = 4,DATABITS = 8read_bufferBusy parity_errorbuffer_fullONERxdata[7:0] data_rx[15:0]resetclockwriteONETxPerform a behavioural simulation of the top-level simulation test-module (test_TxRxSysRTL), afterthe simulation has initially run for 1 us, add the following internal signals to the wave window,restart the simulation and rerun until the ‘$stop’ command is executed in the test-module.Transmitter: TxState, BT and BC.Receiver: RxState, BT, BC and Start.Capture and paste an image of the full extent of the simulation waveforms into your report,ensuring all top-level and added internal signal names are legible at the left-hand side. Add asuitable caption to the image and comment on the results.[10 marks]Zoom in to the waveforms in order to enclose a single data character (between two consecutive‘write’ pulses).Capture and paste an image of the single character waveforms into your report, ensuring all toplevel and added internal signal names are legible at the left-hand side. Add a suitable caption tothe image. Confirm that the data value appearing at the ‘data_rx’ port, coincident with theassertion of the ‘buffer_full’ receiver output, matches the value applied to the ‘data’ port of thetransmitter, during the ‘write’ operation.Pan across the waveforms to check that each value transmitted is correctly received by the‘RxSysRTL’ module correctly.[5 marks]Zoom in to the waveforms to enclose an individual data bit (1 or 0). The values of the internalstates and counters should be readable (set radix to unsigned decimal for the latter). Place thecursor on the waveform to show at what point the receiver shift register is loaded with the valuepresent on ‘RxIn’.Capture and paste an image of the waveforms into your report, ensuring all top-level and addedinternal signal names are legible at the left-hand side. Add a suitable caption to the image.Measure the width of the data-bit using the cursors and markers in the wave window, comment onthe value recorded.[5 marks]Modify the source descriptions of the test-module and/or DUT to demonstrate the correctbehaviour of the ‘parity_error’ output of the receiver. Capture appropriate waveforms anddocument the changes made to the sources. Briefly explain the operation of the parity error circuit.[5 marks]Task 3 – Add the remaining sources to the Vivado RTL projectGo to the eLearning portal and locate the ‘XADC Display (SV)’ item in the ‘Week 4’ folder ofmodule KD7020(EN0720), as shown in the image below.Download both the PDF and ZIP file onto your student-drive and extract all files from the archiveinto your Vivado project folder.Compare the diagram on page 1 of the file ‘XADC_Display_SV_2019.pdf’ with figure 3 above, it isevident that some of the source files are common to both designs:• XADC_Controller.sv – requires modification, rename the file and module as‘XADC_Controller_tx’.• Timer.sv – identical• bcd2seg.sv – identical• DispCntr.sv – identical• DispMux.sv – replace with provided source.• testbench.sv – requires modification, no need to change the file and module name.• Basys3_XADC_RTL.xdc – requires modification, rename the file as‘Basys3_XADC_TxSys_RxSys_Display.xdc’• XADC_RTL_Display.sv – requires modification, rename the file and module as‘XADC_TxSys_RxSys_Display’. This is the top-level design source.Prior to adding the above files to your Vivado project, rename those source files indicated above,the required changes to the source descriptions can be made after the files have been added tothe project. All source files, apart from ‘testbench.sv’ are for both simulation and implementation(i.e. design sources), whereas ‘testbench’ is for simulation only.The ‘XADC’ IP module, instantiated within the top-level design, must be regenerated by means ofthe ‘IP Catalog’ in the Flow Navigator, by following the procedure described in the document‘XADC_Display_SV_2019.pdf’.Once all files have been added to the project, and the XADC module regenerated and embeddedinto the top-level module, capture an image of the ‘Sources’ window from within the PROJECTMANAGER. It may be necessary to float the panel out in order to view the entire design andsimulation hierarchy. Note that the design hierarchy view will depend upon whether or not therequired modifications to the source files have been made, therefore this image should becaptured once the changes carried out in Task 4 have been made.[5 marks]Task 4.1 – Modify the ‘XADC_Controller_tx’ modulePage 28 of the ‘XADC_Display_SV_2019.pdf’ document shows the existing ASM chart for thecontrol block ‘XADC_Controller’. As shown in figure 3 (3a) above, an additional output, named‘write’, is required to drive the ‘write’ input of the transmitter module ‘TxSysRTL’.The ‘write’ signal is to be asserted during an additional state named ‘TRANS’ that is enteredunconditionally from the ‘GET_DATA’ state. Note that ‘write’ is a direct output that occurs duringstate ‘TRANS’, it is not a register transfer.The added state ‘TRANS’ leads unconditionally back to the ‘WT_TRIG’ state.Figure 3a also shows an additional modification of the ‘XADC_Controller_tx’ is required. The ‘data’output port is 12-bits rather than 16-bits wide. In the ‘GET_DATA’ state, the most-significant 12-bits of the XADC output data (do_out) is to be transferred to the ‘data’ output register.Draw a modified ASM chart for the ‘XADC_Controller_tx’ module, showing the additional state andmodified register transfer described above. Include a copy of the modified ASM chart in yourreport.[5 marks]Include a full listing of the modified ‘XADC_Controller_tx.sv’ module source in your report,presented in a style similar to that used in Appendix A and highlighting the changes you havemade (consolas font, reserved words bold, comments in italics with appropriate use ofindentation). Do not use a screen-copy of the listing as it appears within the Vivado text editor.[10 marks]Task 4.2 – Complete the top-level design module source description‘XADC_TxSys_RxSys_Display.sv’.Compare figure 3 on page 4 of this document (XADC_TxSys_RxSys_Display) with the diagram onpage 2 of the ‘XADC_Display_SV_2019.pdf’ document (XADC_RTL_Display). The majordifference between the two systems is the addition of the bit-serial transmitter and receivermodules to the design.Study figure 3 carefully and make the necessary modifications to the SV source file‘XADC_TxSys_RxSys_Display.sv’, adding the extra input/output ports and internal signalsassociated with the communications channel along with the instantiations of the ‘TxSysRTL’ and‘RxSysRTL’ modules. Add a continuous assignment to describe the multiplexer that selectsbetween the timer-generated and manual trigger pulses (‘Auto_Man’ input). Make use of the SVautomatic port connection feature in order to shorten and simplify the net-list.Include a full listing of the modified ‘XADC_TxSys_RxSys_Display.sv’ module source in yourreport, presented in a style similar to that used in Appendix A (consolas font, reserved wordsbold, comments in italics with appropriate use of indentation). Do not use a screen-copy of thelisting as it appears within the Vivado text editor.[10 marks]Task 5 – Modify the simulation test-module source file ‘testbench.sv’.The Verilog-HDL test-module imported from the ‘XADC_Display_SV_2019’ project requiresmodification for use with the top-level module developed in Task 4.2.The main changes are as follows: i.Add identically named declarations of input and output signals for the ‘TxSysRTL’and ‘RxSysRTL’ modules along with the ‘Auto_Man’ selection input (use type logic).Add a continuous assignment to connect the transmitter output to the receiver input,‘TxOut’ to ‘RxIn’, thereby creating the ‘loop-back’ test.Add sequential statements to the initial block shown below, to create the stimulusii.iii. required to show correct automatic and manual transmission across the link, usingthe waveform extract shown in figure 8.Figure 8 – waveform extract showing timing of test-bench inputs and XADC analogue inputchanges (blue lines).initial beginRESET = 1’b1;..set transmit and receive parity..enable automatic conversions..set ‘read_buffer’ to logic-1repeat (10) @(negedge CLK100M);RESET = 1’b0; repeat (…………) @(negedge CLK100M);..enable manual conversions..delay for around 50us repeat (100) @(negedge CLK100M); repeat (……) beginMan = 1’b1;..perform a few manual conversions repeat (100) @(negedge CLK100M);Man = 1’b0;repeat (600) @(negedge CLK100M);end$stop;endInclude a full listing of the modified ‘testbench.sv’ module source in your report, presented in astyle similar to that used in Appendix A (consolas font, reserved words bold, comments in italicswith appropriate use of indentation). Do not use a screen-copy of the listing as it appears withinthe Vivado text editor.[10 marks]Task 6 – Create the XADC analogue input stimulus file, ‘design.txt’, and perform a functionalsimulation of the top-level design module using the ‘testbench’ module.Table 1 shows the values and times for the simulated analogue voltages applied to the vaux[6]input channel.The values change at intervals of 5us (apart from the first change to 0.1), this matches the ‘Timer’parameter ‘NUMCLKS’, which is set to 500 for simulation.Copy the contents of Table 1 in order to create the ‘design.txt’ stimulus file. Note that this text fileis used during the configuration of the XADC IP block.Table 1 – Contents of design.txt fileRun a Behavioural Simulation of the top-level simulation test-module. Add the following signals tothe Wave window in the vertical order shown (delete any signals that are not in the list):/testbench/UUT/RESET/testbench/UUT/CLK100M/testbench/UUT/Man/testbench/UUT/Auto_Man/testbench/UUT/MP/testbench/UUT/trigger/testbench/UUT/convst_in/testbench/UUT/eoc_out/testbench/UUT/den_in/testbench/UUT/drdy_out/testbench/UUT/write/testbench/UUT/do_out/testbench/UUT/data/testbench/UUT/Busy/testbench/UUT/TxData/testbench/UUT/RxIn/testbench/UUT/buffer_full/testbench/UUT/data_rx/testbench/UUT/parity_error/testbench/UUT/AN0/testbench/UUT/AN1/testbench/UUT/AN2/testbench/UUT/AN3/testbench/UUT/bcd/testbench/UUT/DMUX1/data_reg/testbench/UUT/sel/testbench/UUT/CON1/pstateSet the radix of any bus signals appropriately, usually hexadecimal, and change colours to attemptto make the waveforms more readable.Capture a number of alternative views of the waveforms (full, zoomed-in etc.) and add them toyour assignment document with captions and comments. Use the waveforms to confirm correctoperation of all parts of the system, from the timer triggering a conversion of the analogue inout ,to the display of the equivalent digital value in hexadecimal format on the 4-digit display.[15 marks]Task 7 – Complete the Design Constraints file ‘Basys3_XADC_TxSys_RxSys_Display.xdc’,implement the design and configure the Basys3 FPGA BoardAfter renaming the existing Xilinx Design Constraint file, ‘Basys3_XADC_RTL.xdc’, as‘Basys3_XADC_TxSys_RxSys_Display.xdc’, and adding it to the project, edit the file so that alltop-level inputs and outputs are associated with the correct physical FPGA pin numbers. TIMEVAUXP[6]VAUXN[6]000000.00.0100000.10.0150000.40.0200000.30.0250000.920.0300000.490.0350000.330.0400000.250.0450000.750.0 Refer to figure 3 for details of all pin numbers, these are shown in parentheses ‘( )’ next to eachport name.Some of the pins used in the top-level design module are already included in the constraint file (forexample, the display pins). Those that are missing must be uncommented and edited, see belowfor an example:set_property PACKAGE_PIN W2 [get_ports read_buffer]set_property IOSTANDARD LVCMOS33 [get_ports read_buffer]set_property PACKAGE_PIN U1 [get_ports ONERx]set_property IOSTANDARD LVCMOS33 [get_ports ONERx]Include a listing in your report of the contents of the completed‘Basys3_XADC_TxSys_RxSys_Display.xdc’, file. Unused FPGA pins may be deleted in order toshorten the listing, highlight the changes/additions required for the present design.Change any module instance parameters to those that are compatible with implementation (Timerand Display Counter). Copy the changes into your assignment report and comment.Run the Vivado Implementation process and capture a screen image to show successfulimplementation.Generate the Bit-stream file and use the Hardware Manager to configure the Basys3 FPGA board.Capture images showing correct operation of the system using your smartphone (you can measurethe analogue input voltage using a DVM if available).There may be an opportunity to do a practical demonstration of the design in the laboratory. Tryconnected two Basys3 boards together and transmit from one to the other.[10 marks][Total Part 1: 120 marks]File ‘En0720_KD7020_assignment_part1_2020_21.docx’, September 2020.Part 1 marksTask 1 – 20Task 2 – 10, 10, 5, 5, 5Task 3 – 5Task 4.1 – 5, 10Task 4.2 – 10Task 5 – 10Task 6 – 15Task 7 – 10Total for Part 1 = 120 marksAppendix A – SystemVerilog Source ListingsSource file ‘TxSysRTL.sv’`timescale 1ns / 1psmodule TxSysRTL #(parameter CLKSPERBIT = 18, BITSPERCHAR = 11,BTn = 5, BCn = 4, DATABITS = 8)(input logic clock, reset, odd_noteven, write,input logic [DATABITS-1:0] data,output logic Busy,output logic TxData);//RTL Statestypedef enum logic [1:0] {IDLE = 0, S1, S2, S3} state_t;var state_t TxState;logic [BITSPERCHAR-1:0] SR;//Bit timer and bit counterlogic [BTn-1:0] BT;logic [BCn-1:0] BC;logic parity;assign parity = odd_noteven ^ (^data);//next state sequential logicalways_ff @(posedge clock, posedge reset)begin : NStateif(reset == 1’b1)TxState

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