Multi-FSM Design and Analysis Problems | My Assignment Tutor

ECE 465, Spring 2021, Instructor: Prof. Shantanu DuttProject 2, Part IDue: (a) Part I (Single FSM and Multi-FSM Design and Analysis Problems—Section 2) on Fri 04/30,11:59 pm. (b) Part II (to be provided in a separate document): Entire project on Sat 05/08, 11:59 pmImportant Grading Notes:(1) Grading of all parts including the design part is conditioned on the correctness of your simulated design.This means that if your design produces correct results for only an α fraction of the input data provided toyou, the maximum points achievable in each portion of this project will be scaled to an α fraction of itsoriginal points. That is, if your design does works correctly on only 60% of the inputs, a part has 200 pointsallocated to it, and if you get x ≤ 200 points for it, you will obtain 0:6x as your final points for that part.(2) Specify the number of inputs (among all inputs provided to you by the TA) for which your Quartustiming simulation provides correct outputs for both designs (multi-FSM and combinational) at the topof your report (just after the report title, and team member names).1 GoalsThe goals of this project are:1. The project is to be done in groups of 4.2. To design:(a) A single Moore FSM design for adding two n-bit numbers A; B, inputted to the FSM 2 bits at atime for each of A; B, LSB first; assume n is even. The sum bits (2 bits produced every cc afteran initial lag of 1-2 cc’s) and the final carry-out bit Cout are stored via an n-bit shift register SR2that shifts 2 bits right every cc.A designated 2-member sub-group should do this design and this sub-group should bespecified beforehand and also mentioned in the report.(b) A multi-Moore-FSM design (each a simpler FSM than the aforementioned single FSM) forperforming the same function as above, and which also employs the DAC strategy for resolvingthe carry-dependency between bit i and i + 1 additions, where i is even and 0 ≤ i < n – 1.In conjunction with an all-FSM design at most two 1-bit 2:1 mux’es may be used. No otherextra combinational circuit beyond those inherent in the synthesis of the FSMs is to be used.The FSMs can provide some inputs to each other via their output(s), i.e., besides being parallel1FSMs, they can also be interacting FSMs.A second designated 2-member sub-group (disjoint from the first sub-group) should dothis design and this sub-group should be specified beforehand and also mentioned in thereport.3. To synthesize the two FSM designs using the one-hot design style, and implement and simulate themusing Quartus for n = 16.4. Comparison of Clock periods Tclk, m the number of cc’s needed to add the two n bit numbers (m ≥n=2 but should be close to n=2), and total time T = m × Tclk (via Quartus design and timingsimulations).5. There will be no Design Vision part for this project.2 Part I: Design Problem (1500 points)The block and timing diagrams for the system is shown in Fig.1, and explained below. The 2 bits of A; Bfed to the system in each cc are labeled a; an in increasing order of significance, and b; bn in increasing orderof significance (the n subscript indicates ”next” and is not related to the input size n), respectively. Besidesthese data inputs, the system also has a check bit input c, which when changes from 0 to 1 signals that thethe last 2 bits (MSB and 2nd MSB) of A and B appeared on a; an, and b; bn, respectively, in the previous cc.Otherwise c = 0 when valid bits of A; B are inputted in the current add computation.. Thus in cc k on theappearance of c = 1 (after c = 0 in the previous cc k – 1), the system can go to the reset state(s) to wait forthe next A; B pair which will be signaled by c going from 1 to 0.Also, starting from the cc after the one in the 1st set of valid bits are inputted on a; an; b; bn, the twocorresponding sum bits s; sn (in increasing order of significance) are to be loaded into the 2 MSB bits ofthe n-bit 2-bit shifting register SR2; SR2 also simultaneously shifts its current bits, including in the 2 MSBpositions 2 bits to the right. The final carry-out Cout needs to be in the Cout 1-bit register (D-FF).1. Provide a well-derived and explained design of the single-FSM Moore and mult-FSM Moore systems(the state-transition diagrams) mentioned above. 50%2. Provide their 1-hot based synthesis. Each state should be labeled by its meaning or what past inputinformation class it remembers. 20%3. Theoretically analyze for the two designs: (a) FF cost (number of D-FFs); (b) gate-input unit basedlogic cost of the two designs (though you need not provide a detailed gate-level design as that wouldbe too messy, but you should be able to estimate the gate sizes needed, e.g., a 1-to-2k demux has2Figure 1: (a) Block diagram of FSM-based adder design. (b) Timing diagram for input data streaming andbasic input control signal.2k (k + 1)-input AND gates and k NOT gates); (c) the crtitical path delays across both next-stateand output logic modules, based on gate input units, where assume that FF delay = 4 gate input units(again, a detailed gate-level design).After the detailed analysis/derivation, the comparison of the aforementioned parameters should bedone via a well-structured table(s), and then rationale conclusions should be drawn about the pros andcons of the two designs based on the comparisons. 30%3


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