DEU Nominative Integrated Automatic Computer (DEUNIAC) Design | My Assignment Tutor

DEU Nominative Integrated AutomaticComputer (DEUNIAC) DesignCME 2206 Computer Architecture 2020-2021 Term Project Image: Colossus Source: 2206 – LAB PROJECTDESCRIPTIONYou will design a basic computer that called DEUNIAC (DEU Nominative Integrated AutomaticComputer). DEUNIAC has nine registers, three memories, arithmetic and logic unit, control unitand bus system.Quartus II software will be used to design and verify DEUNIAC. The project is given as a termproject and will be implemented in weekly lab sessions. It is advised that you read problemdefinitions of all of them before actually starting to implement your design, i.e., Common Bus andRegisters.Please submit zipped All Files (don’t forget to submit waveform of the results and screenshots) ofthe simulations for each lab session.GENERAL STRUCTURE OF DEUNIACREGISTERSDEUNIAC has 9 registers which are Address Register, Program Counter, Stack Pointer, InputRegister, Output Register, Instruction Register and 3 general purpose registers.MEMORIESIn DEUNIAC, there are two memories, which are instruction (32×11), data (16×4) and stack (16×5)Each has “read enable” signals and “data inputs”. Data and stack memory also has “write enableinput”.COMMON BUS SYSTEMCommon bus system will be responsible for data flow and provide data transfer between registerand/or memories.ARITHMETIC AND LOGIC UNITIn ALU, arithmetic and logical operations will be held.CONTROL UNITControl unit processes instructions to direct the micro-operations for computer’s memories,registers and arithmetic/logic unit. Control unit consists of decoders and a number of control logicgates. It should produce operation signals and time periods for fetching, decoding and executing theinstructions.ASSIGNMENT 3 – CONTROL UNITDEUNIAC has three instruction code formats as shown in the Table 1 – DEUNIAC InstructionSet. The type of the instruction recognized by the computer control unit using four-bits opcodes.You should generate a list for the control function and microoperations of DEUNIAC (as Table 5.6of Mano’s Basic Computer) before designing control unit. Control unit includes logical designs tocontrol registers, memories, common bus and ALU. Figure 1 and Figure 2 show general view ofcontrol unit design and DEUNIAC respectively. But they haven’t to be completed or correct, soyou may add or change signals, components etc. in your designs.Table 1 – DEUNIAC Instruction Set SymbolDescriptionOperationOpcodeHLT0111Halt the computerArithmetic and Logic OperationsQ(1 bit) Opcode (4 bits) Rd (2 bits) S1 (2 bits) S2 (2 bits)DBL0000Double content of S1 and store the result in RdDBT0001Divide content of S1 by 2 and store result to RdADD0010Add content of S1 and S2 and store result in RdINC0011Increase content of S1 and store result in RdAND0100AND contents of S1 and S2 and store result in RdNOT0101Complement content of S1 and store the result in RdXOR0110XOR contents of S1 and S2 and store result in RdData TransferQ(1 bit) Opcode (4 bits) Rd (2 bits) S1 (2 bits) S2 (2 bits)ST1000Write the content of Rd into the memory of address S1S2 if Q=0Write the data S1S2 into the memory of address indicated by the content of register Rd if Q=1LD1001Read the data S1S2 and load it into Rd, if Q=0Read the memory content of address S1S2 and load it into Rd, if Q=1IO1010Transfer data from register that is indicated by S1 into OUTR, if Q=0 Registers: 00 R0, 01 R1, 10 R2Transfer data from INPR into register that is indicated by Rd, if Q=1 Registers: 00 R0, 01 R1, 10 R2TSF1011Transfer data from register that is indicated by S1 into Rd.Registers: 00 R0, 01 R1, 10 R2Program ControlQ(1 bit) Opcode (4 bits) -(1 bit) Address (5 bits)JMP1100if Q=0 then jumps to address (5-bits)if Q=1 and if V=1 then jumps to address (5-bits) (V is overflow flag)CAL1101go to the address of the instruction memory (PUSH operation of stack memory)RET1110load the previous PC content from the stack into PC (POP operation of stack memory)JMR1111X(1 bit) Opcode (4 bits) XX (2 bits) Address (4 bits – signed)Use Address as offset and jump to address relatively Figure 1 – General structure of Control Unit in DEUNIAC 109 8 7 65-0 4×16 Decoder15 14 … 0… Q(n-1) … 1 0n x 2n Decoder…Increment (INR)T(n-1)…RegistersControlMemoryControlBUSControlALUControlCONTROL LOGIC GATES n-bit sequencecounter (SC)15 14 … 0 Clear (CLR)Clock (CLK)Instruction RegisterFigure 2 – General view of DEUNIACMUX-EPC (5-bits) InstructionMemory(ROM)LDINRCLRCLKSAddrS1S2SEInstruction memoryunit AR (4-bits) DataMemory(RAM)LDCLRCLKS1S2SP (4-bits) Stack Memory(RAM) CLRDCRCLKINRMRMWSRSWPC ( 5 bits) Control UnitOPDCRsS1S2 MRMWSWSRLDsCLRsINRSDSESCSBSAInOutALU CommonBUSSystem Data memory unitStack memory unit ABSASBSCSD OPRVOther Inputs


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